Civil Engineering Project Manager Job at Nederveld, Inc., Grand Rapids, MI

SVFsemNlaFhKN09HSngxcnNhM3paY2l1R3c9PQ==
  • Nederveld, Inc.
  • Grand Rapids, MI

Job Description

This role will guide a land development project through collaboration with a group of civil engineers, land planners, landscape architects, and CAD designers as well as some civil site design for land development projects.

Essential Functions

  • Effectively manage multiple land development projects simultaneously
  • Civil design for residential, commercial, and municipal projects
  • Participate in site visits, agency meetings, and municipal meetings
  • Ensure effective communication with all team members and clients

Essential Skills for Performing the Job

  • Self-motivated
  • Detail oriented
  • Problem-solving
  • Effective communication
  • Professionalism

Required Education and Experience

  • Bachelors of Science in Civil Engineering
  • 5-7 years of private land development civil engineering design
  • 1-2 years of AutoCAD Civil 3D

Other Requirements

  • Licensed Professional Engineer

Position Type/Expected Hours

This is a full-time position. Some flexibility in hours is permitted, but s/he must be available during the standard work hours of 8:00 AM to 5:00 PM.

Physical Demands

This position is a combination of sedentary work, with some field and travel-related work. An employee is regularly required to stand, sit, walk, reach, type, talk, hear, balance, stoop, kneel, crouch, crawl, climb, push, pull, carry, and lift. An employee may also be required to drive, traverse wooded and/or uneven terrain, enter structures, use ladders, walk on roofs, enter small spaces, and work in various weather conditions.

Travel

Some travel to and from project sites, municipal and agency offices, client offices, and other Nederveld offices, is to be expected.

Disclaimer

Please note this position description is not designed to cover or contain a comprehensive listing of activities, duties, or responsibilities that are required of the employee for this job. Duties, responsibilities, and activities are subject to change.

Eligible candidates will be legally authorized to work in the United States without employment visa sponsorship.

Nederveld Inc. is an Equal Opportunity Employer.

Job Tags

Full time, Visa sponsorship, Work visa,

Similar Jobs

TSG - The Sheridan Group

Offset Press Assistant I Job at TSG - The Sheridan Group

Sheridan. Be part of something greater. Your career awaitsjoin us!As one of the leading print and publishing service providers in the nation, Sheridan prints everything from popular novels to prestigious education and trades books, and so much more.?A career at Sheridan... 

Helen Ross McNabb Center

UTMC Emergency Department Case Manager Job at Helen Ross McNabb Center

 ...UTMC Emergency Department Case Manager Help Others, Make a Difference, Save a Life. Do you want to make a difference in people's lives every day? Or help people navigate the tough spots in their life? And do it all while working where your hard work is appreciated... 

Fit Pro Finders

Fitness Coach Job at Fit Pro Finders

Company Description Fit Pro Finders specializes in sourcing talent for entry-level to management positions in the fitness industry. We offer consultative services to support hiring managers in finding exceptional candidates and also provide executive search services...

Wheezy’s Cleanique Services

Janitor Job at Wheezy’s Cleanique Services

 ...Wheezys Cleanique Services in Orange Park, FL is looking for a part-time janitor to join our 27 person strong team. We are located on 283 College Dr. Shift times will vary as it is event based. Our ideal candidate is attentive, punctual, and hard-working. Will be a 10... 

Cadence

Principal FPGA Design Engineer - FPGA IPs (R48198/rj) Job at Cadence

 ...pre-silicon platform for early software development, system validation, and hardware regressions. Protium is leading product in FPGA Emulation/Prototyping domain. This role is to design, verification, timing closure and hardware validation of the FPGA IPs....